1. Field of the Invention
The invention relates to a voltage regulator, and in particular to a voltage regulator having fast response to abrupt load transients.
2. Description of the Related Art
FIG. 1 shows a voltage regulator as disclosed in U.S. Pat. No. 6,201,375. The voltage regulator 100 comprises an error amplifier 102, an output transistor (power NMOS transistor) 104, a feedback circuit comprising resistors R1 and R2, a comparator 106, a transistor (NMOS transistor) 108 and an output capacitor CL. The voltage source 105 is the input offset voltage VOFS of the comparator 106. The comparator 106 and the NMOS transistor 108 form a local load transient suppression loop which specially deals with a load condition while the voltage regulator 100 suffers from heavy load to light load. When loading of the voltage regulator 100 changes from heavy to light, the output regulated voltage VOUT suffers an abrupt rise (or overvoltage). Hence, the feedback voltage VFB is also increased. When the feedback voltage VFB exceeds the sum of the reference voltage VREF and the input offset voltage VOFS, the comparator 106 turns on the NMOS transistor 108 to sink currents, thereby reducing the overvoltage of the output regulated voltage VOUT. More particularly, when the output voltage VOUT exceeds the reference voltage VREF by a voltage
            V      OFS        ×                            R          1                +                  R          2                            R        1              ,the load transient suppression loop is activated to control the overvoltage of the output regulated voltage VOUT.
Generally, electronic systems adopting a voltage regulator are more sensitive to undervoltage of the regulated output voltage than overvoltage of the regulated output voltage. The voltage regulator suffers undervoltage of its output regulated voltage when its loading changes from light to heavy. For example, the output regulated output VOUT of the voltage regulator 100 is supplied to an electronic system (not shown in FIG. 1). When the electronic system is in a power-off or standby state, i.e. with a light load, the output transistor 104 outputs a considerably small current. When the electronic system switches to a power-on state, i.e. with a heavy load, the voltage regulator 100 must supply large current to the electronic system. However, the output transistor 104 cannot supply current suddenly to satisfy the large current requirement, and thus the voltage regulator 100 cannot respond rapidly enough to compensate the output undervoltage of the output regulated voltage VOUT.
Generally, in order to increase current supplied from the output transistor 104, the gate voltage of the output transistor 104 should be pulled up by the feedback loop path of the voltage regulator 100, through the feedback circuit (R1 and R2), the error amplifier 102 and the output transistor 104. Unfortunately, transient response of the feedback loop path is very slow due to compensation stability. In addition, the output transistor 104 (power NMOS transistor) is often large and thus has a large gate capacitance, resulting in speed limitation when charging the gate voltage of the output transistor 104. An added buffer stage with increased bias current may speed the response of the output transistor 104, but current consumption of the voltage regulator 100 is then increased and feedback loop delay still remains.